1. Field of the Invention
The present invention relates to improvements of a well structure employed in semiconductor memory devices such as dynamic random access memories (DRAMs).
2. Description of the Background Art
FIG. 12 is a block diagram of the structure of a DRAM. A schematic structure of the DRAM will now be described with reference to FIG. 12. The DRAM generally includes a memory cell array portion serving as a storage region for storing a great deal of information and a peripheral circuit portion required for external inputs/outputs.
The memory cell array portion includes a memory cell portion 51 for storing data signals of the storage information, a row decoder 53 and a column decoder 54 for designating a memory cell constituting a unit storage circuit, and a sense refresh amplifier 55 for amplifying a signal stored in the designated memory cell, to read the amplified signal.
The peripheral circuit portion includes a row and column address buffer 52 for receiving an externally applied address signal for selecting memory cells, a data-in buffer 56 and a data-out buffer 57 employed for data inputs/outputs, a clock generator 58 for generating a clock signal, and the like.
FIG. 13 is a cross-sectional structural diagram schematically showing a well structure of the DRAM. A plurality of p well regions P.sub.1 and P.sub.2 and a plurality of n well regions N.sub.1 and N.sub.2 are formed in a p type silicon substrate 1. In the memory cell array portion, for example, nMOS switching transistors of memory cells or the like are, mainly formed in p well region P.sub.1, and pMOS transistors of sense amplifiers or the like are formed in n well region N.sub.1. In the peripheral circuit portion, similarly, nMOS transistors constituting various circuits are formed in p well region P.sub.2 , and pMOS transistors are formed in n well region N.sub.2. p well regions P.sub.1 and P.sub.2 have their potentials held at a ground potential V.sub.SS, and n well regions N.sub.1 and N.sub.2 have their potentials held at a supply potential V.sub.CC.
The above-described well structure held at a predetermined potential has a problem of the occurrence of undershoot of an input signal at an input terminal. FIG. 14 is a diagram showing changes in the signal potential of an input signal Vin from an input terminal connected to p well region P.sub.2 of FIG. 13. Referring to FIGS. 13 and 14, when the logic level of input signal Vin from the input terminal changes from a logic high level to a 0 level, there is a case where so-called undershoot occurs in which the potential of the input signal instantaneously decreases to a negative potential below the 0 level. In this case, in p well region P.sub.2, a well potential is held at V.sub.SS (=0), so that if an input potential becomes a negative potential, a large number of electrons are instantaneously injected from the input terminal into silicon substrate 1. The electrons injected into the substrate flow into, for example, an adjacent p well region P.sub.1 and further into a capacitor 12 of a memory cell through a source/drain region 11 formed in p well region P.sub.1. Thus, the level of a logic high level signal stored in capacitor 12 changes to a logic low level, thereby destroying data.
This undershoot occurs not only at the input terminal but also at internal input terminals of a peripheral circuit or a decoder and a sense amplifier.
In order to avoid such undershoot, a method is provided, for example, in which the potential of a p well region is set to a negative potential V.sub.BB which allows for more margins as compared with the potential for undershoot. Such a state that the potential of the p well region is set to the negative potential is shown in FIG. 15. FIG. 15 is a cross-sectional structural view of a semiconductor memory device corresponding to FIG. 13. p well region P.sub.1 of the memory cell array portion and p well region P.sub.2 of the peripheral circuit portion are each held at the negative potential V.sub.BB. Holding p well regions P.sub.1 and P.sub.2 at the negative potential V.sub.BB can prevent the injection of electrons from the input terminal even if undershoot from the input terminal is developed, and can also prevent data destruction of memory cells or the like. In this method, however, a new problem occurs in which the characteristics of an nMOS transistor formed in a well region set in the negative potential V.sub.BB are deteriorated. That is, if a gate length of the MOS transistor formed in this well region set in the negative potential V.sub.BB is reduced, then a decrease in a threshold voltage depending on the gate length becomes significant as compared with the case where the well potential is set to V.sub.SS, and a decrease in a breakdown voltage developed across the source and the drain becomes significant. Accordingly, with the capacity of the DRAM becoming larger and the structure thereof becoming smaller, the characteristics of MOS transistors become significantly deteriorated. It is thus difficult to set the potential of the p well region to the negative potential V.sub.BB.